A standard, commonly accepted high-speed optical link block diagram is shown in FIG. 1, which is often referred to as a Serializer/Deserializer (SerDes). A signal to be transmitted is prepared in the digital signal processor on the transmitter side (DSP TX). The signal is then applied to the optical transmitter driver, modulator driver (E/O TX). The optical transmitter (Optical TX) sends the optical signal into the fiber/waveguide and on the receive side the optical signal is converted back into the electrical domain by the optical receiver (Optical RX), amplified by the transimpedance amplifier (E/O RX) and finally it is processed by the receiver DSP (DSP RX).
Depending on the application and the performance requirements of the link this general architecture can have many different implementation variants, but the overall structure remains largely the same. The DSP input/output (I/O) front end is analog. It can be implemented, for example, as an explicit digital to analog converter (DAC) on the TX side and an analog to digital converter (ADC) on the RX side. The algorithms implemented in the DSP can be general purpose or specific for the particular optical technology being used. Regardless of the link application and type of the coding scheme, a part of the DSP computational power is often used for equalization. For example, some versions of the DSP attempt to correct for the imperfections of the fiber, the optical-optical (0-0) part of the link. At high speeds, the relatively long electrical link E-E becomes a limiting factor and the TX/RX DSP applies equalization to correct for that. In all of these scenarios, the job of the E/O TX and E/O RX components remains the same: to faithfully convert the electrical data into the optical domain, and to convert the optical data back into the electrical domain. As a result, high bandwidth requirements are usually imposed on the E/O TX, the Optical TX, the Optical RX and the E/O RX. At high data rates, driving the Optical TX with a full bandwidth driver becomes a significant challenge, often dramatically increasing power dissipation in the E/O TX. The situation is even more dramatic on the receive side, where the bandwidth requirements and the receiver sensitivity are in a direct trade off. In addition, the high bandwidth requirement is placing a significant burden on the design and fabrication of the optical components, the Optical TX and the Optical RX.
At the same time, it is well known that equalization can be used to correct for bandwidth limitations of the transimpedance amplifier (TIA) in the E/O RX. Some papers, for example, propose placing a continuous time linear equalizer (CTLE) after a low bandwidth TIA. See for example D. Li, et al., “A Low-Noise Design Technique for High-Speed CMOS Optical Receivers,” IEEE J. Solid-State Circuits, vol. 49, no. 6, pp. 1437-1447, June 2014.
Others have argued in favor of the benefits of the decision-feedback equalizer (DFE). See for example A. Rylyakov et al., “A new ultra-high sensitivity, low-power optical receiver based on a decision-feedback equalizer,” Proc. Optical Fiber Communications Conf. (OFC), paper OThP3, March 2011. This approach, however, requires monolithic integration of the O/E RX functions with the RX DSP on a single chip, which is not always the best solution from the cost and power dissipation point of view. Also, it addresses only the receiver part of the link, and still requires the use of a high bandwidth transmitter.
There is a need for improved optical link apparatus and methods of operation.